verilog - Is it a bad practice to reset a variable in one model using a variable from another model? - Stack Overflow

I'm building a vending machine. I want the pay sum to maintain its value until the candy is out or canceled.

To simplify, is it ok to build a reset this way:

module m1(
  input clk,
  input m2_reset,
  output enough_payment);
   
  always@(posedge clk, posedge m2_reset) begin
    if (m2_reset) begin
        payment<=0;
        enough_payment<=0; end
    else if(payment<=CANDY_PRICE) begin //collect money while the payment is not enough
            payment<= coin_5*5 + coin_10*10; 
            enough_payment<=0; end 
         else // payment will be equal to CANDY_PRICE and maybe a little extra
            enough_payment<=1;  
  end
endmodule

module m2(
  input clk, enough_payment,
  output m2_reset);

  always@(posedge clk) begin
    if(enough_payment)
        if(counter==RANDOM_NUM)
           m2_reset<=1;
        else begin
           m2_reset<=0;
           counter<=counter+1; 
  end
endmodule

I'm building a vending machine. I want the pay sum to maintain its value until the candy is out or canceled.

To simplify, is it ok to build a reset this way:

module m1(
  input clk,
  input m2_reset,
  output enough_payment);
   
  always@(posedge clk, posedge m2_reset) begin
    if (m2_reset) begin
        payment<=0;
        enough_payment<=0; end
    else if(payment<=CANDY_PRICE) begin //collect money while the payment is not enough
            payment<= coin_5*5 + coin_10*10; 
            enough_payment<=0; end 
         else // payment will be equal to CANDY_PRICE and maybe a little extra
            enough_payment<=1;  
  end
endmodule

module m2(
  input clk, enough_payment,
  output m2_reset);

  always@(posedge clk) begin
    if(enough_payment)
        if(counter==RANDOM_NUM)
           m2_reset<=1;
        else begin
           m2_reset<=0;
           counter<=counter+1; 
  end
endmodule

• verilog
• system-verilog
• fpga

Share Improve this question Follow edited Jan 2 at 20:12 toolic 62.5k2121 gold badges7979 silver badges128128 bronze badges asked Jan 2 at 19:43 Ilan MermelsteinIlan Mermelstein 2544 bronze badges

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1 Answer 1

Sorted by: Reset to default 2

Assuming you directly connect the m2_reset signals to each other at the upper level of the design hierarchy, this should be fine.

In m1, m2_reset is used as an asynchronous reset. Since it is a registered output of m2, there will be no glitches on it. That is good design practice.